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w WM8776 24-bit, 192khz stereo codec with 5 channel i/p multiplexer wolfson microelectronics plc w :: www.wolfsonmicro.com product preview, june 2004, rev 1.91 copyright ? 2004 wolfson microelectronics plc description the WM8776 is a high performance, stereo audio codec with five channel input selector. the WM8776 is ideal for surround sound processing applications for home hi-fi, dvd-rw and other audio visual equipment. a stereo 24-bit multi-bit sigma delta adc is used with a five stereo channel input mixer. each adc channel has programmable gain control with automatic level control. digital audio output word lengths from 16-32 bits and sampling rates from 32khz to 96khz are supported. a stereo 24-bit multi-bit sigma delta dac is used with digital audio input word lengths from 16-32 bits and sampling rates from 32khz to 192khz. the dac has an input mixer allowing an external analogue signal to be mixed with the dac signal. there are also headphone and line outputs, with volume controls for the headphones. the WM8776 supports fully independent sample rates for the adc and dac. the audio data interface supports i 2 s, left justified, right justified and dsp formats. the device is controlled in software via a 2 or 3 wire serial interface, selected by the mode pin, which provides access to all features including channel selection, volume controls, mutes, and de-emphasis facilities. the device is available in a 48-pin tqfp package. features ? audio performance ? 108db snr (a weighted @ 48khz) dac ? 102db snr (a weighted @ 48khz) adc ? dac sampling frequency: 32khz C 192khz ? adc sampling frequency: 32khz C 96khz ? five stereo adc inputs with analogue gain adjust from +24db to C21db in 0.5db steps ? programmable limiter or automatic level control (alc) ? stereo dac with independent analogue and digital volume controls ? stereo headphone and line output ? 3-wire spi compatible or 2-wire software serial control interface ? master or slave clocking mode ? programmable audio data interface modes ? i 2 s, left, right justified or dsp ? 16/20/24/32 bit word lengths ? analogue bypass path feature ? selectable aux input to the volume controls ? 2.7v to 5.5v analogue, 2.7v to 3.6v digital supply operation applications block diagram ? surround sound av processors and hi-fi systems ? dvd-rw z hpoutl hpoutr stereo adc agnd avdd vmidadc audio interface and digital filters adclrc dacbclk daclrc din dout stereo dac ain2r ain3l ain3r ain4l ain4r ain5l ain5r ainopr ainopl ainvgr ainvgl adcrefp dacrefp dacrefn vmiddac dvdd dgnd control interface auxl auxr di ce cl mode dacmclk ain2l ain1r ain1l w WM8776 adcmclk adcbclk low pass filters adcrefgnd voutl voutr alc input mixer vmid hpvdd hpgnd zflagl zflagr
WM8776 product preview w pp rev 1.91 june 2004 2 table of contents description .......................................................................................................1 features.............................................................................................................1 applications .....................................................................................................1 block diagram .................................................................................................1 table of contents .........................................................................................2 pin configuration...........................................................................................3 ordering information ..................................................................................3 pin description ................................................................................................4 absolute maximum ratings.........................................................................5 electrical characteristics ......................................................................6 terminology ............................................................................................................ 7 master clock timing......................................................................................8 digital audio interface C master mode ......................................................... 9 digital audio interface C slave mode .......................................................... 10 3-wire mpu interface timing ............................................................................ 11 control interface timing C 2-wire mode .................................................... 12 device description .......................................................................................13 introduction ......................................................................................................... 13 audio data sampling rates............................................................................... 14 zero detect ........................................................................................................... 15 powerdown modes ............................................................................................. 15 power-on-reset ................................................................................................... 16 digital audio interface ..................................................................................... 17 control interface operation ........................................................................ 21 control interface registers ........................................................................ 23 limiter / automatic level control (alc) ...................................................... 32 register map ......................................................................................................... 39 digital filter characteristics ...............................................................47 dac filter responses......................................................................................... 47 adc filter responses......................................................................................... 48 adc high pass filter ........................................................................................... 49 digital de-emphasis characteristics........................................................... 50 applications information .........................................................................51 external circuit configuration ................................................................... 51 recommended external components ..................................................52 package dimensions ....................................................................................54 address: .................................................................................................................. 55
product preview WM8776 w pp rev 1.91 june 2004 3 pin configuration ordering information device temperature range package moisture sensitivity level peak soldering temperature WM8776eft/v -25 to +85 o c 48-pin tqfp msl2 240 c WM8776eft/rv -25 to +85 o c 48-pin tqfp (tape and reel) msl2 240 c WM8776seft/v -25 to +85 o c 48-pin tqfp (lead free) msl2 260 c WM8776seft/rv -25 to +85 o c 48-pin tqfp (lead free, tape and reel) msl2 260 c note: reel quantity = 2,200
WM8776 product preview w pp rev 1.91 june 2004 4 pin description pin name type description 1 ain2l analogue input channel 2 left input multiplexor virtual ground 2 ain1r analogue input channel 1 right input multiplexor virtual ground 3 ain1l analogue input channel 1 left input multiplexor virtual ground 4 dacbclk digital input/output dac audio interface bit clock 5 dacmclk digital input master dac clock; 256, 384, 512 or 768fs (fs = word clock frequency) 6 din digital input dac data input 7 daclrc digital input/output dac left/right word clock 8 zflagr open drain output dac right zero flag output (external pull-up resistor required) 9 zflagl open drain output dac left zero flag output (external pull-up resistor required) 10 adcbclk digital input/output adc audio interface bit clock 11 adcmclk digital input adc audio interface master clock 12 dout digital output adc data output 13 adclrc digital input/output adc left/right word clock 14 dgnd supply digital negative supply 15 dvdd supply digital positive supply 16 mode digital input control interface mode select (5v tolerant) 17 ce digital input serial interface latch signal (5v tolerant) 18 di digital input serial interface data (5v tolerant) 19 cl digital input serial interface clock (5v tolerant) 20 hpoutl analogue output headphone left channel output 21 hpgnd supply headphone negative supply 22 hpvdd supply headphone positive supply 23 hpoutr analogue output headphone right channel output 24 nc not bonded 25 nc not bonded 26 voutl analogue output dac channel left output 27 voutr analogue output dac channel right output 28 vmiddac analogue output dac midrail decoupling pin ; 10uf external decoupling 29 dacrefn analogue input dac negative reference input 30 dacrefp analogue input dac positive reference input 31 auxr analogue input dac mixer right channel input 32 auxl analogue input dac mixer left channel input 33 vmidadc analogue output adc midrail divider decoupling pin; 10uf external decoupling 34 adcrefgnd supply adc negative supply and substrate connection 35 adcrefp analogue output adc positive reference decoupling pin; 10uf external decoupling 36 avdd supply analogue positive supply 37 agnd supply analogue negative supply and subvstrate connection 38 ainvgr analogue input right channel multiplexor virtual ground 39 ainopr analogue output right channel multiplexor output 40 ainvgl analogue input left channel multiplexor virtual ground 41 ainopl analogue output left channel multiplexor output 42 ain5r analogue input channel 5 right input multiplexor virtual ground 43 ain5l analogue input channel 5 left input multiplexor virtual ground 44 ain4r analogue input channel 4 right input multiplexor virtual ground 45 ain4l analogue input channel 4 left input multiplexor virtual ground 46 ain3r analogue input channel 3 right input multiplexor virtual ground 47 ain3l analogue input channel 3 left input multiplexor virtual ground 48 ain2r analogue input channel 2 right input multiplexor virtual ground note : digital input pins have schmitt trigger input buffers and pins 16, 17, 18 and 19 are 5v tolerant.
product preview WM8776 w pp rev 1.91 june 2004 5 absolute maximum ratings absolute maximum ratings are stress ratings only. permanent damage to the device may be caused by continuously operating at or beyond these limits. device functional operating limits and guaranteed performance specifications are given under electrical characteristics at the test conditions specified. esd sensitive device. this device is manufactured on a cmos process. it is therefore generically susceptible to damage from excessive static voltages. proper esd precautions must be taken during handling and storage of this device. wolfson tests its package types according to ipc/jedec j-std-020b for moisture sensitivity to determine acceptable storage conditions prior to surface mount assembly. these levels are: msl1 = unlimited floor life at <30 c / 85% relative humidity. not normally stored in moisture barrier bag. msl2 = out of bag storage for 1 year at <30 c / 60% relative humidity. supplied in moisture barrier bag. msl3 = out of bag storage for 168 hours at <30 c / 60% relative humidity. supplied in moisture barrier bag. condition min max digital supply voltage -0.3v +3.63v analogue supply voltage -0.3v +7v voltage range digital inputs (di, cl, ce and mode) dgnd -0.3v +7v voltage range digital inputs (mclk, din, adclrc, daclrc, adcbclk and dacbclk) dgnd -0.3v dvdd + 0.3v voltage range analogue inputs agnd -0.3v avdd +0.3v master clock frequency 37mhz operating temperature range, t a -25 c +85 c storage temperature -65 c +150 c notes: 1. analogue and digital grounds must always be within 0.3v of each other. recommended operating conditions parameter symbol test conditions min typ max unit digital supply range dvdd 2.7 3.6 v analogue supply range avdd, hpvdd, dacrefp 2.7 5.5 v ground agnd, dgnd, dacrefn, adcrefgnd 0 v difference dgnd to agnd -0.3 0 +0.3 v note: digital supply dvdd must never be more than 0.3v greater than avdd.
WM8776 product preview w pp rev 1.91 june 2004 6 electrical characteristics test conditions avdd = 5v, dvdd = 3.3v, agnd = 0v, dgnd = 0v, t a = +25 o c, fs = 48khz, mclk = 256fs unless otherwise stated. parameter symbol test conditions min typ max unit digital logic levels (ttl levels) input low level v il 0.8 v input high level v ih 2.0 v output low v ol i ol =1ma 0.1 x dvdd v output high v oh i oh =1ma 0.9 x dvdd v analogue reference levels reference voltage v vmid avdd/2 v potential divider resistance r vmid 50k ? dac performance (load = 10k ? , 50pf) 0dbfs full scale output voltage 1.0 x avdd/5 vrms snr (note 1,2) a-weighted, @ fs = 48khz 108 db snr (note 1,2) a-weighted @ fs = 96khz 108 db dynamic range (note 2) dnr a-weighted, -60db full scale input 108 db total harmonic distortion (thd) 1khz, 0dbfs -97 -90 db dac channel separation 100 db 1khz 100mvpp 50 db power supply rejection ratio psrr 20hz to 20khz 100mvpp 45 db headphone buffer maximum output voltage 0.9 vrms r l = 32 ? 25 mw max output power (note 4) p o r l = 16 ? 50 mw snr (note 1,2) a-weighted 85 92 db headphone analogue volume gain step size 0.5 1 1.5 db headphone analogue volume gain range 1khz input -73 +6 db headphone analogue volume mute attenuation 1khz input, 0db gain 100 db 1khz, r l = 32 ? @ p o = 10mw rms -80 0.01 -60 0.1 db % total harmonic distortion +noise thd+n 1khz, r l = 32 ? @ p o = 20mw rms -77 0.014 -40 1.0 db % power supply rejection ratio psrr 20hz to 20khz, without supply decoupling -40 db adc performance input signal level (0db) 1.0 x avdd/5 vrms snr (note 1,2) a-weighted, 0db gain @ fs = 48khz 102 db snr (note 1,2) a-weighted, 0db gain @ fs = 96khz 64 x osr 100 db dynamic range (note 2) a-weighted, -60db full scale input 102 db total harmonic distortion (thd) 1khz, 0dbfs -90 -80 db
product preview WM8776 w pp rev 1.91 june 2004 7 test conditions avdd = 5v, dvdd = 3.3v, agnd = 0v, dgnd = 0v, t a = +25 o c, fs = 48khz, mclk = 256fs unless otherwise stated. 1khz, -3dbfs -95 -85 db adc channel separation 1khz input 90 db programmable gain step size 0.25 0.5 0.75 db programmable gain range (analogue) 1khz input -21 +24 db programmable gain range (digital) 1khz input -103 -21.5 db mute attenuation (note 6) 1khz input, 0db gain 76 db 1khz 100mvpp 50 db power supply rejection ratio psrr 20hz to 20khz 100mvpp 45 db analogue input (ain) to analogue output (vout) (load=10k ? , 50pf, gain = 0db) bypass mode 0db full scale output voltage 1.0 x avdd/5 vrms snr (note 1) 90 100 db 1khz, 0db -90 db thd 1khz, -3db -95 db 1khz 100mvpp 50 db power supply rejection ratio psrr 20hz to 20khz 100mvpp 45 db mute attenuation 1khz, 0db 100 db supply current analogue supply current avdd = 5v 48 ma digital supply current dvdd = 3.3v 8 ma notes: 1. ratio of output level with 1khz full scale input, to the output level with all zeros into the digital input, measured a weighted. 2. all performance measurements done with 20khz low pass filter, and where noted an a-weight filter. failure to use such a filter will result in higher thd+n and lower snr and dynamic range readings than are found in the electrical characteristics. the low pass filter removes out of band noise; although it is not audible it may affect dynamic specification values. 3. vmid decoupled with 10uf and 0.1uf capacitors (smaller values may result in reduced performance). 4. harmonic distortion on the headphone output decreases with output power. 5. all performance measurement done using certain timings conditions (please refer to section digital audio interface). 6. a better mute attenuation can be achieved if the adc gain is set to minimum. terminology 1. signal-to-noise ratio (db) - snr is a measure of the difference in level between the full scale output and the output with no signal applied. (no auto-zero or automute function is employed in achieving these results). 2. dynamic range (db) - dnr is a measure of the difference between the highest and lowest portions of a signal. normally a thd+n measurement at 60db below full scale. the measured signal is then corrected by adding the 60db to it. (e.g. thd+n @ -60db= -32db, dr= 92db). 3. thd+n (db) - thd+n is a ratio, of the rms values, of (noise + distortion)/signal. 4. stop band attenuation (db) - is the degree to which the frequency spectrum is attenuated (outside audio band). 5. channel separation (db) - also known as cross-talk. this is a measure of the amount one channel is isolated from the other. normally measured by sending a full scale signal down one channel and measuring the other. 6. pass-band ripple - any variation of the frequency response in the pass-band region.
WM8776 product preview w pp rev 1.91 june 2004 8 master clock timing mclk t mclkl t mclkh t mclky figure 1 master clock timing requirements test conditions avdd = 5v, dvdd = 3.3v, agnd = 0v, agnd, dgnd = 0v, t a = +25 o c, fs = 48khz, adc/dacmclk = 256fs unless otherwise stated. parameter symbol test conditions min typ max unit system clock timing information adc/dacmclk system clock pulse width high t mclkh 11 ns adc/dacmclk system clock pulse width low t mclkl 11 ns adc/dacmclk system clock cycle time t mclky 28 ns adc/dacmclk duty cycle 40:60 60:40 table 1 master clock timing requirements
product preview WM8776 w pp rev 1.91 june 2004 9 digital audio interface C master mode adcbclk dout adclrc din daclrc WM8776 codec dvd controller dacbclk figure 2 audio interface - master mode adcbclk/ dacbclk (output) dout adclrc/ daclrc (outputs) t dl din t dda t dht t dst figure 3 digital audio data timing C master mode test conditions avdd = 5v, dvdd = 3.3v, agnd, dgnd = 0v, t a = +25 o c, master mode, fs = 48khz, adc/dacmclk = 256fs unless otherwise stated. parameter symbol test conditions min typ max unit audio data input timing information adc/daclrc propagation delay from adc/dacbclk falling edge t dl 0 10 ns dout propagation delay from adcbclk falling edge t dda 0 10 ns din setup time to dacbclk rising edge t dst 10 ns din hold time from dacbclk rising edge t dht 10 ns table 2 digital audio data timing C master mode
WM8776 product preview w pp rev 1.91 june 2004 10 digital audio interface C slave mode adcbclk dout adclrc din daclrc WM8776 codec dvd controller dacbclk figure 4 audio interface C slave mode adcbclk/ dacbclk daclrc/ adclrc t bch t bcl t bcy din dout t lrsu t ds t lrh t dh t dd figure 5 digital audio data timing C slave mode test conditions avdd = 5v, dvdd = 3.3v, agnd = 0v, dgnd = 0v, t a = +25 o c, slave mode, fs = 48khz, adc/dacmclk = 256fs unless otherwise stated. parameter symbol test conditions min typ max unit audio data input timing information adc/dacbclk cycle time t bcy 50 ns adc/dacbclk pulse width high t bch 20 ns adc/dacbclk pulse width low t bcl 20 ns daclrc/adclrc set-up time to adc/dacbclk rising edge t lrsu 10 ns daclrc/adclrc hold time from adc/dacbclk rising edge t lrh 10 ns din set-up time to dacbclk rising edge t ds 10 ns din hold time from dacbclk rising edge t dh 10 ns dout propagation delay from adcbclk falling edge t dd 0 10 ns table 3 digital audio data timing C slave mode note: adclrc and daclrc should be synchronous with mclk, although the WM8776 interface is tolerant of phase variations or jitter on these signals.
product preview WM8776 w pp rev 1.91 june 2004 11 3-wire mpu interface timing ce cl di t csl t dho t dsu t csh t scy t sch t scl t scs lsb t css figure 6 spi compatible (3-wire) control interface input timing (mode=1) test conditions avdd = 5v, dvdd = 3.3v, agnd, dgnd = 0v, t a = +25 o c, fs = 48khz, mclk = 256fs unless otherwise stated parameter symbol min typ max unit cl rising edge to ce rising edge t scs 60 ns cl pulse cycle time t scy 80 ns cl pulse width low t scl 30 ns cl pulse width high t sch 30 ns di to cl set-up time t dsu 20 ns cl to di hold time t dho 20 ns ce pulse width low t csl 20 ns ce pulse width high t csh 20 ns ce rising to cl rising t css 20 ns table 4 3-wire spi compatible control interface input timing information
WM8776 product preview w pp rev 1.91 june 2004 12 control interface timing C 2-wire mode t 3 t 1 t 6 t 9 t 2 t 5 t 7 t 3 t 4 t 8 di cl figure 7 control interface timing C 2-wire serial control mode (mode=0) test conditions avdd = 5v, dvdd = 3.3v, agnd, dgnd = 0v, t a = +25 o c, fs = 48khz, mclk = 256fs unless otherwise stated parameter symbol min typ max unit program register input information cl frequency 0 400 khz cl low pulse-width t 1 600 ns cl high pulse-width t 2 1.3 us hold time (start condition) t 3 600 ns setup time (start condition) t 4 600 ns data setup time t 5 100 ns di, cl rise time t 6 300 ns di, cl fall time t 7 300 ns setup time (stop condition) t 8 600 ns data hold time t 9 900 ns pulse width of spikes that will be suppressed t ps 0 5 ns table 5 2-wire control interface timing information.
product preview WM8776 w pp rev 1.91 june 2004 13 device description introduction WM8776 is a complete 2-channel dac, 2-channel adc audio codec, with flexible input multiplexor including digital interpolation and decimation filters, multi-bit sigma delta stereo adc, and switched capacitor multi-bit sigma delta dacs with analogue volume controls on each channel and output smoothing filters. it is available in a single package and controlled by either a 3-wire or 2-wire software interface. the 3-wire interface is compatible with the spi standard. an analogue bypass path option is available, to allow stereo analogue signals from any of the 5 stereo inputs to be sent to the stereo outputs via the main volume controls. this allows a purely analogue input to analogue output high quality signal path to be implemented if required. the dac and adc have separate left/right clocks, bit clocks, master clocks and data i/os. the audio interface may be configured to operate in either master or slave mode. in slave mode adclrc, daclrc, adcbclk and dacbclk are all inputs. in master mode adclrc, daclrc, adcbclk and dacbclk are outputs. the input multiplexor to the adc is configured to allow large signal levels to be input to the adc, using external resistors to reduce the amplitude of larger signals to within the normal operating range of the adc. the adc has an analogue input pga and a digital gain control, accessed by one register write. the input pga allows input signals to be gained up to +24db and attenuated down to -21db in 0.5db steps. the digital gain control allows attenuation from -21.5db to -103db in 0.5db steps. this allows the user maximum flexibility in the use of the adc. the dac has its own digital volume control, which is adjustable between 0db and -127.5db in 0.5db steps. there is also an analogue volume control on the headphone outputs, which is adjustable between +6db and -73db in 1db steps. the analogue and digital volume controls may be operated independently. in addition a zero cross detect circuit is provided for both analogue and digital volume controls. when analogue volume zero-cross detection is enabled the attenuation values are only updated when the input signal to the gain stage is close to the analogue ground level. the digital volume control detects a transition through the zero point before updating the volume. this minimises audible clicks and zipper noise as the gain values change. the dac output incorporates an input selector and mixer allowing a signal to be either switched into the signal path in place of the dac signal or mixed with the dac signal before the volume control. use of external resistors allows larger input levels to be accepted by the device, giving maximum user flexibility. internal functionality is controlled by ce, cl, di and mode input pins. these are 5v tolerant with ttl input thresholds, allowing the wm 8776 to used with dvdd = 3.3v and be controlled by a controller with 5v output. the mode pin determines which of the two control interface modes is selected. operation using system clock of 128fs, 192fs, 256fs, 384fs, 512fs or 768fs is provided. in slave mode selection between clock rates is automatically controlled. in master mode the master clock to sample rate ratio is set by control bits adcrate and dacrate. adc and dac may run at different rates and have their own bit clocks and master clocks. the audio data interface supports right, left and i 2 s interface formats along with a highly flexible dsp serial port interface.
WM8776 product preview w pp rev 1.91 june 2004 14 audio data sampling rates in a typical digital audio system there is only one central clock source producing a reference clock to which all audio data processing is synchronised. this clock is often referred to as the audio systems master clock. the WM8776 uses separate master clocks for the adc and dac. the external master system clocks can be applied directly through the adcmclk and dacmclk input pins with no software configuration necessary. in a system where there are a number of possible sources for the reference clock it is recommended that the clock source with the lowest jitter be used to optimise the performance of the adc and dac. the master clock for WM8776 supports dac and adc audio sampling rates from 256fs to 768fs, where fs is the audio sampling frequency (daclrc or adclrc) typically 32khz, 44.1khz, 48khz or 96khz (the dac also supports operation at 128fs and 192fs and 192khz sample rate). the master clock is used to operate the digital filters and the noise shaping circuits. in slave mode the WM8776 has a master detection circuit that automatically determines the relationship between the master clock frequency and the sampling rate (to within +/- 32 system clocks). if there is a greater than 32 clocks error the interface is disabled and maintains the output level at the last sample. the master clock should be synchronised with adclrc/daclrc for optical performance, although the WM8776 is tolerant of phase variations or jitter on this clock. table 6 shows the typical master clock frequency inputs for the WM8776. the signal processing for the WM8776 typically operates at an oversampling rate of 128fs for both adc and dac. the exception to this for the dac is for operation with a 128/192fs system clock, e.g. for 192khz operation where the oversampling rate is 64fs. for adc operation at 96khz it is recommended that the user set the adcosr bit. this changes the adc signal processing oversample rate to 64fs. system clock frequency (mhz) 128fs 192fs sampling rate (daclrc/ adclrc) dac only 256fs 384fs 512fs 768fs 32khz 4.096 6.144 8.192 12.288 16.384 24.576 44.1khz 5.6448 8.467 11.2896 16.9340 22.5792 33.8688 48khz 6.144 9.216 12.288 18.432 24.576 36.864 96khz 12.288 18.432 24.576 36.864 unavailable unavailable 192khz 24.576 36.864 unavailable unavailable unavailable unavailable table 6 system clock frequencies versus sampling rate in master mode dacbclk, adcbclk, daclrc and adclrc are generated by the WM8776. the frequencies of adclrc and daclrc are set by setting the required ratio of dacmclk to daclrc and adcmclk to adclrc using the dacrate and adcrate control bits (table 7). adcrate[2:0]/ dacrate[2:0] adcmclk/dacmclk: adclrc/daclrc ratio 000 128fs (dac only) 001 192fs (dac only) 010 256fs 011 384fs 100 512fs 101 768fs table 7 master mode mclk:adclrc/daclrc ratio select
product preview WM8776 w pp rev 1.91 june 2004 15 table 8 shows the settings for adcrate and dacrate for common sample rates and adcmclk/dacmclk frequencies. system clock frequency (mhz) 128fs 192fs 256fs 384fs 512fs 768fs sampling rate (daclrc/ adclrc) dacrate =000 dacrate =001 adcrate/ dacrate =010 adcrate/ dacrate =011 adcrate/ dacrate =100 adcrate/ dacrate =101 32khz 4.096 6.144 8.192 12.288 16.384 24.576 44.1khz 5.6448 8.467 11.2896 16.9340 22.5792 33.8688 48khz 6.144 9.216 12.288 18.432 24.576 36.864 96khz 12.288 18.432 24.576 36.864 unavailable unavailable 192khz 24.576 36.864 unavailable unavailable unavailable unavailable table 8 master mode adc/daclrc frequency selection adcbclk and dacbclk are also generated by the WM8776. the frequency of adcbclk and dacbclk depends on the mode of operation. in 128/192fs modes (dacrate=000 or 001) bclk = mclk/2. in 256/384/512fs modes (adcrate/dacrate=010 or 011 or 100) bclk = mclk/4. however if dsp mode is selected as the audio interface mode then bclk=mclk. note that dsp mode cannot be used in 128fs mode for word lengths greater than 16 bits or in 192fs mode for word lengths greater than 24 bits. zero detect the WM8776 has a zero detect circuit for each dac channel, which detects when 1024 consecutive zero samples have been input. the two zero flag outputs (zflagl and zflagr) may be programmed to output the zero detect signals (see table 9) that may then be used to control external muting circuits. a 1 on zflagl or zflagr indicates a zero detect. the zero detect may also be used to automatically enable the pga mute by setting izd. the zero flag output may be disabled by setting dzfm to 00. the zero flag signal for each dac channel will only be enabled if it is enabled as an input to the output summing stage. dzfm[1:0] zflagl zflagr 00 zero flag disabled zero flag disabled 01 left channel zero right channel zero 10 both channel zero both channel zero 11 either channels zero either channel zero table 9 zero flag output select powerdown modes the WM8776 has powerdown control bits allowing specific parts of the WM8776 to be powered off when not being used. the 5-channel input source selector and input buffer may be powered down using control bit ainpd. when ainpd is set all inputs to the source selector (ain1l/r to ain5l/r) are switched to a buffered vmidadc. control bit adcpd powers off the adc and also the adc input pgas. the stereo dac has a separate powerdown control bit, dacpd allowing the dac and analogue output mixer to be powered off when not in use. this also switches the analogue outputs voutl/r to vmiddac to maintain a dc level on the output. setting ainpd, adcpd and dacpd will powerdown everything except the references vmidadc, adcref and vmiddac. these may be powered down by setting pdwn. setting pdwn will override all other powerdown control bits. it is recommended that ainpd, hppd, adcpd and dacpd are set before setting pdwn. the default is for all blocks to be enabled other than hppd.
WM8776 product preview w pp rev 1.91 june 2004 16 power-on-reset the WM8776 has an internal power-on-reset circuit. the reset phase is entered at power-up of supplies. the dac and adc dsp circuitry is also reset when their respective master clocks are stopped. register values are maintained unless either a power-on-reset occurs or a software reset is written. a software reset will also cause a reset of the dac and adc dsp. figure 8 shows the power-on-reset logic, and figure 9 shows the reset release characteristics. figure 8 circuit diagram for power-on-reset figure 9 timing diagram for power on sequence
product preview WM8776 w pp rev 1.91 june 2004 17 digital audio interface master and slave modes the audio interface operates in either slave or master mode, selectable using the ms control bit. in both master and slave modes din is always an input to the WM8776 and dout is always an output. the default is slave mode. in slave mode (ms=0) adclrc, daclrc, adcbclk and dacbclk are inputs to the WM8776 (figure 10). din and daclrc are sampled by the WM8776 on the rising edge of dacbclk, adclrc is sampled on the rising edge of adcbclk. adc data is output on dout and changes on the falling edge of adcbclk. by setting control bit bclkinv the polarity of adcbclk and dacbclk may be reversed so that din and daclrc are sampled on the falling edge of dacbclk, adclrc is sampled on the falling edge of adcbclk and dout changes on the rising edge of adcbclk. adcbclk dout adclrc din daclrc WM8776 codec dvd controller dacbclk figure 10 slave mode in master mode (ms=1) adclrc, daclrc, adcbclk and dacbclk are outputs from the WM8776 (figure 11). adclrc, daclrc, adcbclk and dacbclk are generated by the WM8776. din is sampled by the WM8776 on the rising edge of dacbclk so the controller must output dac data that changes on the falling edge of dacbclk. adc data is output on dout and changes on the falling edge of adcbclk. by setting control bit bclkinv, the polarity of adcbclk and dacbclk may be reversed so that din is sampled on the falling edge of dacbclk and dout changes on the rising edge of adcbclk. adcbclk dout adclrc din daclrc WM8776 codec dvd controller dacbclk figure 11 master mode
WM8776 product preview w pp rev 1.91 june 2004 18 audio interface formats audio data is applied to the internal dac filters or output from the adc filters, via the digital audio interface. 5 popular interface formats are supported: ? left justified mode ? right justified mode ? i 2 s mode ? dsp early mode ? dsp late mode all 5 formats send the msb first and support word lengths of 16, 20, 24 and 32 bits, with the exception of 32 bit right justified mode, which is not supported. in left justified, right justified and i 2 s modes, the digital audio interface receives dac data on the din input and outputs adc data on dout. audio data for each stereo channel is time multiplexed with adclrc/daclrc indicating whether the left or right channel is present. adclrc/daclrc is also used as a timing reference to indicate the beginning or end of the data words. in left justified, right justified and i 2 s modes; the minimum number of bclks per daclrc/adclrc period is 2 times the selected word length. adclrc/daclrc must be high for a minimum of word length bclks and low for a minimum of word length bclks. any mark to space ratio on adclrc/daclrc is acceptable provided the above requirements are met. in dsp early or dsp late mode, daclrc is used as a frame sync signal to identify the msb of the first word. the minimum number of dacbclks per daclrc period is 2 times the selected word length. any mark to space ratio is acceptable on daclrc provided the rising edge is correctly positioned. the adc data may also be output in dsp early or late modes, with adclrc used as a frame sync to identify the msb of the first word. the minimum number of adcbclks per adclrc period is 2 times the selected word length. left justified mode in left justified mode, the msb of din is sampled by the WM8776 on the first rising edge of dacbclk following a daclrc transition. the msb of the adc data is output on dout and changes on the same falling edge of adcbclk as adclrc and may be sampled on the rising edge of adcbclk. adclrc and daclrc are high during the left samples and low during the right samples (figure 12). left channel right channel daclrc/ adclrc dacbclk/ adcbclk din/ dout 1/fs n 3 2 1 n-2 n-1 lsb msb n 3 2 1 n-2 n-1 lsb msb figure 12 left justified mode timing diagram
product preview WM8776 w pp rev 1.91 june 2004 19 right justified mode in right justified mode, the lsb of din is sampled by the WM8776 on the rising edge of dacbclk preceding a daclrc transition. the lsb of the adc data is output on dout and changes on the falling edge of adcbclk preceding a adclrc transition and may be sampled on the rising edge of adcbclk. adclrc and daclrc are high during the left samples and low during the right samples (figure 13). left channel right channel daclrc/ adclrc dacbclk/ adcbclk din/ dout 1/fs n 3 2 1 n-2 n-1 lsb msb n 3 2 1 n-2 n-1 lsb msb figure 13 right justified mode timing diagram i 2 s mode in i 2 s mode, the msb of din is sampled by the WM8776 on the second rising edge of dacbclk following a daclrc transition. the msb of the adc data is output on dout and changes on the first falling edge of adcbclk following an adclrc transition and may be sampled on the rising edge of adcbclk. adclrc and daclrc are low during the left samples and high during the right samples. left channel right channel daclrc/ adclrc dacbclk/ adcbclk din/ dout 1/fs n 3 2 1 n-2 n-1 lsb msb n 3 2 1 n-2 n-1 lsb msb 1 bclk 1 bclk figure 14 i 2 s mode timing diagram dsp early mode in dsp early mode, the msb of dac left data is sampled by the WM8776 on the second rising edge on dacbclk following a daclrc rising edge. dac right data follows dac channel left data (figure 15).
WM8776 product preview w pp rev 1.91 june 2004 20 daclrc dacbclk din word length (wl) 1/fs left channel n 2 1 n-1 lsb msb n 2 1 n-1 right channel no valid data 1 bclk 1 bclk figure 15 dsp early mode timing diagram C dac data input the msb of the left channel adc data is output on dout and changes on the first falling edge of adcbclk following a low to high adclrc transition and may be sampled on the rising edge of adcbclk. the right channel adc data is contiguous with the left channel data (figure 16) adclrc adcbclk dout word length (wl) 1/fs left channel n 2 1 n-1 lsb msb n 2 1 n-1 right channel no valid data 1 bclk 1 bclk figure 16 dsp early mode timing diagram C adc data output dsp late mode in dsp late mode, the msb of dac left data is sampled by the WM8776 on the first dacbclk rising edge following a daclrc rising edge. dac right follow dac left data (figure 17). daclrc dacbclk din word length (wl) 1/fs left channel n 2 1 n-1 lsb msb n 2 1 n-1 right channel no valid data 1 figure 17 dsp late mode timing diagram C dac data input
product preview WM8776 w pp rev 1.91 june 2004 21 the msb of the left channel adc data is output on dout and changes on the same falling edge of adcbclk as the low to high adclrc transition and may be sampled on the rising edge of adcbclk. the right channel adc data is contiguous with the left channel data (figure 18). adclrc adcbclk dout word length (wl) 1/fs left channel n 2 1 n-1 lsb msb n 2 1 n-1 right channel no valid data 1 figure 18 dsp late mode timing diagram C adc data output in both early and late dsp modes, the left channel is always sent first, followed immediately by the right channel. no dacbclk edges are allowed between the data words. control interface operation the WM8776 is controlled by writing to registers through a serial control interface. a control word consists of 16 bits. the first 7 bits (b15 to b9) are address bits that select which control register is accessed. the remaining 9 bits (b8 to b0) are data bits, corresponding to the 9 bits in each control register. the control interface can operate as either a 3-wire or 2-wire mpu interface. the mode pin selects the interface format, as shown in table 10. . mode control mode 0 2 wire interface 1 3 wire interface table 10 control interface selection via mode pin the control interface is 5v tolerant, meaning that the control interface input signals ce, cl and di as well as mode may have an input high level of 5v while dvdd is 3v. input thresholds are determined by dvdd. 3-wire (spi compatible) serial control mode in 3-wire mode, every rising edge of cl clocks in one data bit from the di pin. a rising edge on ce latches in a complete control word consisting of the last 16 bits. the 3-wire interface protocol is shown in figure 19. figure 19 3-wire spi compatible interface b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 di cl ce control register address control register data bits latch
WM8776 product preview w pp rev 1.91 june 2004 22 b[15:9] are control address bits b[8:0] are control data bits ce is edge sensitive C the data is latched on the rising edge of ce. 2-wire serial control mode the WM8776 supports software control via a 2-wire serial bus. many devices can be controlled by the same bus, and each device has a unique 7-bit address (this is not the same as the 7-bit address of each register in the WM8776). the WM8776 operates as a slave device only. the controller indicates the start of data transfer with a high to low transition on di while cl remains high. this indicates that a device address and data will follow. all devices on the 2-wire bus respond to the start condition and shift in the next eight bits on di (7-bit address + read/write bit, msb first). if the device address received matches the address of the WM8776 and the r/w bit is 0, indicating a write, then the WM8776 responds by pulling di low on the next clock pulse (ack). if the address is not recognised or the r/w bit is 1, the WM8776 returns to the idle condition and wait for a new start condition and valid address. once the WM8776 has acknowledged a correct address , the controller s ends the first byte of control data (b15 to b8, i.e. the WM8776 register address plus the first bit of register data). the WM8776 then acknowledges the first data byte by pulling di low for one clock pulse. the controller then sends the second byte of control data (b7 to b0, i.e. the remaining 8 bits of register data), and the WM8776 acknowledges again by pulling di low. the transfer of data is complete when there is a low to high transition on di while cl is high. after receiving a complete address and data sequence the WM8776 returns to the idle state and waits for another start condition. if a start or stop condition is detected out of sequence at any point during data transfer (i.e. di changes while cl is high), the device jumps to the idle condition. figure 20 2-wire serial interface b[15:9] are control address bits b[8:0] are control data bits the WM8776 has two possible device addresses, which can be selected using the ce pin. ce state device address low 0011010 (0 x 34h) high 0011011 (0 x 36h) table 11 2-wire mpu interface address selection
product preview WM8776 w pp rev 1.91 june 2004 23 control interface registers digital audio interface control register interface format is selected via the fmt[1:0] register bits: register address bit label default description r10 (0ah) 0001010 dac interface control 1:0 dacfmt [1:0] 10 r11 (0bh) 0001011 adc interface control 1:0 adcfmt [1:0] 10 interface format select 00 : right justified mode 01: left justified mode 10: i 2 s mode 11: dsp (early or late) mode in left justified, right justified or i 2 s modes, the lrp register bit controls the polarity of adclrc/daclrc. if this bit is set high, the expected polarity of adclrc/daclrc will be the opposite of that shown figure 12, figure 13, etc. note that if this feature is used as a means of swapping the left and right channels, a 1 sample phase difference will be introduced. in dsp modes, the lrp register bit is used to select between early and late modes. register address bit label default description r10 (0ah) 0001010 dac interface control 2 daclrp 0 r11 (0bh) 0001011 adc interface control 2 adclrp 0 in left/right/ i 2 s modes: adclrc/daclrc polarity (normal) 0 : normal adclrc/daclrc polarity 1: inverted adclrc/daclrc polarity in dsp mode: 0 : early dsp mode 1: late dsp mode by default, adclrc, daclrc and din are sampled on the rising edge of adcbclk and dacbclk and should ideally change on the falling edge. data sources that change adclrc/daclrc and din on the rising edge of adcbclk/dacbclk can be supported by setting the bcp register bit. setting bcp to 1 inverts the polarity of bclk to the inverse of that shown in figure 12, figure 13, etc. register address bit label default description r10 (0ah) 0001010 dac interface control 3 dacbcp 0 r11 (0bh) 0001011 adc interface control 3 adcbcp 0 bclk polarity (dsp modes) 0 : normal bclk polarity 1: inverted bclk polarity the wl[1:0] bits are used to control the input word length. register address bit label default description r10 (0ah) 0001010 dac interface control 5:4 dacwl [1:0] 10 r11 (0bh) 0001011 adc interface control 5:4 adcwl [1:0] 10 word length 00 : 16 bit data 01: 20 bit data 10: 24 bit data 11: 32 bit data note: if 32-bit mode is selected in right justified mode, the WM8776 defaults to 24 bits. in all modes, the data is signed 2's complement. the digital filters always input 24-bit data . if the dac is programmed to receive 16 or 20 bit data, the WM8776 pads the unused lsbs with zeros. if the dac is programmed into 32 bit mode, the 8 lsbs are ignored.
WM8776 product preview w pp rev 1.91 june 2004 24 note: in 24 bit i 2 s mode, any width of 24 bits or less is supported provided that adclrc/daclrc is high for a minimum of 24 bclks and low for a minimum of 24 bclks. a number of options are available to control how data from the digital audio interface is applied to the dac. master modes control bit adcms selects between audio interface master and slave modes for adc. in adc master mode adclrc and adcbclk are outputs and are generated by the WM8776. in slave mode adclrc and adcbclk are inputs to WM8776. register address bit label default description r12 (0ch) 0001100 interface control 9 adcms 0 audio interface master/slave mode select for adc: 0 : slave mode 1: master mode control bit dacms selects between audio interface master and slave modes for the dac. in dac master mode daclrc and dacbclk are outputs and are generated by the WM8776. in slave mode daclrc and dacbclk are inputs to WM8776. register address bit label default description r12 (0ch) 0001100 interface control 8 dacms 0 audio interface master/slave mode select for dac: 0 : slave mode 1: master mode master mode adclrc/daclrc frequency select in adc master mode the WM8776 generates adclrc and adcbclk, in dac master mode the WM8776 generates daclrc and dacbclk. these clocks are derived from the master clock (adcmclk or dacmclk). the ratios of adcmclk to adclrc and dacmclk to daclrc are set by adcrate and dacrate respectively. register address bit label default description 2:0 adcrate[2:0] 010 master mode mclk:adclrc ratio select: 010: 256fs 011: 384fs 100: 512fs 101: 768fs r12 (0ch) 0001100 adclrc and daclrc frequency select 6:4 dacrate[2:0] 010 master mode mclk:daclrc ratio select: 000: 128fs 001: 192fs 010: 256fs 011: 384fs 100: 512fs 101: 768fs
product preview WM8776 w pp rev 1.91 june 2004 25 adc oversampling rate select for adc operation at 96khz it is recommended that the user set the adcosr bit. this changes the adc signal processing oversample rate to 64fs. register address bit label default description r12 (0ch) 0001100 adc oversampling rate 3 adcosr 0 adc oversampling rate select 0: 128x oversampling 1: 64x oversampling mute modes setting mute for the dac will apply a soft mute to the input of the digital filters of the channel muted. register address bit label default description r8 (08h) 0001000 dac mute 0 dmute 0 dac soft mute select 0 : normal operation 1: soft mute enabled figure 21 application and release of soft mute figure 21 shows the application and release of dmute whilst a full amplitude sinusoid is being played at 48khz sampling rate. when dmute (lower trace) is asserted, the output (upper trace) begins to decay exponentially from the dc level of the last input sample. the output will decay towards v mid with a time constant of approximately 64 input samples. if dmute is applied to both channels for 1024 or more input samples the dac will be muted if izd is set. when dmute is de-asserted, the output will restart immediately from the current input sample. note that all other means of muting the dac: setting the pl[3:0] bits to 0, setting the pdwn bit or setting attenuation to 0 will cause much more abrupt muting of the output. -2.5 -2 -1.5 -1 -0.5 0 0.5 1 1.5 0 0.001 0.002 0.003 0.004 0.005 0.006 time(s)
WM8776 product preview w pp rev 1.91 june 2004 26 adc mute each adc channel also has an individual mute control bit, which mutes the inpu t to the adc pga. by setting the lrboth bit (reg22, bit 8) both channels can be muted simultaneously. register address bit label default description r21 (15h) 0010101 adc mute left 7 mutela 0 adc mute select 0 : normal operation 1: mute adc left r21 (15h) 0001111 adc mute right 6 mutera 0 adc mute select 0 : normal operation 1: mute adc right de-emphasis mode the de-emphasis filter for the dac is enabled under the control of deemp. register address bit label default description r9 (09h) 0001001 dac de-emphasis control 0 deemph 0 de-emphasis mode select: 0 : normal mode 1: de-emphasis mode refer to figure 34, figure 35, figure 36, figure 37, figure 38 and figure 39 for details of the de-emphasis modes at different sample rates. powerdown mode and adc/dac disable setting the pdwn register bit immediately powers down the WM8776, including the references, overriding all other powerdown control bits. all trace of the previous input samples is removed, but all control register settings are preserved. when pdwn is cleared, the digital filters will be re-initialised. it is recommended that the 5-channel input mux and buffer, adc and dac are powered down before setting pdwn. register address bit label default description r13 (0dh) 0001101 powerdown control 0 pdwn 0 power down mode select: 0 : normal mode 1: power down mode the adc, dac and headphone pgas may also be powered down by setting the adcd and dacd disable bits. setting adcd will disable the adc and select a low power mode. the adc digital filters will be reset and will reinitialise when adcd is reset. the dac has a separate disable dacd. setting dacd will disable the dac, mixer and output pgas. resetting dacd will reinitialise the digital filters. register address bit label default description 1 adcpd 0 adc powerdown: 0 : normal mode 1: power down mode 2 dacpd 0 dac powerdown: 0 : normal mode 1: power down mode r13 (0dh) 0001101 powerdown control 3 hppd 1 headphone output/pga power down : 0 : hp out enabled 1 : hp out disabled the analogue audio inputs and outputs can also be individually powered down by setting the relevant bits in the powerdown register.
product preview WM8776 w pp rev 1.91 june 2004 27 register address bit label default description r13 (0dh) 0001101 powerdown control 6 ainpd 0 analogue input pga disable: 0 : normal mode 1: power down mode digital attenuator control mode setting the atc register bit causes the left channel attenuation settings to be applied to both left and right channel dacs from the next audio input sample. no update to the attenuation registers is required for atc to take effect. register address bit label default description r7 (07h) 0000111 dac channel control 1 atc 0 attenuator control mode: 0 : right channel use right attenuation 1: right channel use left attenuation infinite zero detect enable setting the izd register bit will enable the internal infinite zero detect function: register address bit label default description r7 (07h) 0000111 dac channel control 2 izd 0 infinite zero mute enable 0 : disable infinite zero mute 1: enable infinite zero mute with izd enabled, applying 1024 consecutive zero input samples to the dac will cause both dac outputs to be muted. mute will be removed as soon as any channel receives a non-zero input. dac output control the dac output control word determines how the left and right inputs to the audio interface are applied to the left and right dacs: register address bit label default description pl[3:0] left output right output 0000 mute mute 0001 left mute 0010 right mute 0011 (l+r)/2 mute 0100 mute left 0101 left left 0110 right left 0111 (l+r)/2 left 1000 mute right 1001 left right 1010 right right 1011 (l+r)/2 right 1100 mute (l+r)/2 1101 left (l+r)/2 1110 right (l+r)/2 r7 (07h) 0000111 dac control 7:4 pl[3:0] 1001 1111 (l+r)/2 (l+r)/2
WM8776 product preview w pp rev 1.91 june 2004 28 analogue output volume controls there are analogue volume controls for the headphone outputs which may be adjusted independently using separate volume control registers. register address bit label default description 6:0 hpla[6:0] 1111001 (0db) attenuation data for headphone left channel in 1db steps. see table 13 7 hplzcen 0 headphone left zero cross detect enable 0: zero cross disabled 1: zero cross enabled r0 (00h) 0000000 analogue attenuation headphone output left 8 update not latched controls simultaneous update of headphone attenuation latches 0: store hpla in intermediate latch (no change to output) 1: store hpla and update attenuation on both channels. 6:0 hpla[6:0] 1111001 (0db) attenuation data for headphone right channel in 1db steps. see table 13 7 hprzcen 0 headphone right zero cross detect enable 0: zero cross disabled 1: zero cross enabled r1 (01h) 0000001 analogue attenuation headphone output right 8 update not latched controls simultaneous update of headphone attenuation latches 0: store hpra in intermediate latch (no change to output) 1: store hpra and update attenuation on both channels. 6:0 hpmasta [6:0] 1111001 (0db) attenuation data for both headphone channels in 1db steps. see table 13 7 mzcen 0 master zero cross detect enable 0: zero cross disabled 1: zero cross enabled r2 (02h) 0000010 headphone master analogue attenuation (both channels) 8 updatea not latched controls simultaneous update of attenuation latches 0: store gain in intermediate latch (no change to output) 1: store gain and update attenuation on all channels. r13 (0dh) 0001101 power down 3 hppd 1 headphone output/pga power down 0 : hp out enabled 1 : hp out disabled table 12 headphone attenuation register map each analogue headphone output channel has a pga which can be used to attenuate the output from that channel. the pgas can be powered up or down using the hppd bit. attenuation is 0db by default but can be set between +6db and C73db in 1db steps using the two attenuation control words. the attenuation registers are double latched allowing them to be updated in pairs. setting the update bit on an attenuation write to one channel, for example hpoutl, will cause the pre-latched value in hpoutr to be applied to the pga. a master attenuation register is also included, allowing both volume levels to be set to the same value in a single write. note: the update bit is not latched. if update=0, the attenuation value will be written to the pre-latch but not applied to the pga. if update=1, pre-latched values will be applied from the next input sample. writing to hpmasta[6:0] overwrites any values previously sent to hpla[6:0] and hpra[6:0]. headphone output pga attenuation the analogue output pgas are controlled by the hpla and hpra registers. register bits masta can be used to control attenuation of both channels. table 13 shows how the attenuation levels are selected from the 7-bit words.
product preview WM8776 w pp rev 1.91 june 2004 29 hpla/ hpra[6:0] attenuation level 00(hex) - db (mute) : : 2f(hex) - db (mute) 30(hex) -73db : : 79 (hex) 0db (default) : : 7d(hex) +4db 7e(hex) +5db 7f(hex) +6db table 13 headphone volume control attenuation levels in addition a zero cross detect circuit is provided for the output pga volume under the control of bit 7 (zcen) in the each attenuation register. when zcen is set the attenuation values are only updated when the input signal to the gain stage is close to the analogue ground level. this minimises audible clicks and zipper noise as the gain values change. a timeout clock is also provided which will generate an update after a minimum of 131072 master clocks (= ~10.5ms with a master clock of 12.288mhz). the timeout clock may be disabled by setting tod. register address bit label default description r7 (07h) 0000111 timeout clock disable 3 tod 0 dac and adc analogue zero cross detect timeout disable 0 : timeout enabled 1: timeout disabled dac digital volume control the dac volume may also be adjusted in the digital domain using independent digital attenuation control registers register address bit label default description 7:0 lda[7:0] 11111111 (0db) digital attenuation data for left channel dacl in 0.5db steps. see table 14 r3 (03h) 0000011 digital attenuation dacl 8 updated not latched controls simultaneous update of attenuation latches 0: store lda in intermediate latch (no change to output) 1: store lda and update attenuation on both channels 7:0 rda[6:0] 11111111 (0db) digital attenuation data for right channel dacr in 0.5db steps. see table 14 r4 (04h) 0000100 digital attenuation dacr 8 updated not latched controls simultaneous update of attenuation latches 0: store rda in intermediate latch (no change to output) 1: store rda and update attenuation on both channels. 7:0 mastda[7:0] 11111111 (0db) digital attenuation data for dac channels in 0.5db steps. see table 14 r5 (05h) 0000101 master digital attenuation (both channels) 8 updated not latched controls simultaneous update of attenuation latches 0: store gain in intermediate latch (no change to output) 1: store gain and update attenuation on channels.
WM8776 product preview w pp rev 1.91 june 2004 30 l/rda[7:0] attenuation level 00(hex) - db (mute) 01(hex) -127db : : : : : : fe(hex) -0.5db ff(hex) 0db table 14 digital volume control attenuation levels the digital volume control also incorporates a zero cross detect circuit which detects a transition through the zero point before updating the digital volume control with the new volume. this is enabled by control bit dzcen. register address bit label default description r7 (07h) 0000111 dac control 0 dzcen 0 dac digital volume zero cross enable: 0: zero cross detect disabled 1: zero cross detect enabled dac output phase the dac phase control word determines whether the output of the dac is non-inverted or inverted register address bit label default description bit dac phase 0 dacl 1 = invert r6 (06h) 0000110 dac phase 1:0 ph[1:0] 00 1 dacr 1 = invert adc gain control the adc has an analogue input pga and digital gain control for each stereo channel. both the analogue and digital gains are adjusted by the same register, lag for the left and rag for the right. the analogue pga has a range of +24db to -21db in 0.5db steps. the digital gain control allows further attenuation (after the adc) from -21.5db to -103db in 0.5db steps. table 15 shows how the register maps the analogue and digital gains. lag/rag[7:0] attenuation level (at output) analogue pga digital attenuation 00(hex) - db (mute) -21db digital mute 01(hex) -103db -21db -82db : : : : a4(hex) -21.5db -21db -0.5db a5(hex) -21db -21db 0db : : : : cf(hex) 0db 0db 0db : : : : fe(hex) +23.5db +23.5db 0db ff(hex) +24db +24db 0db table 15 analogue and digital gain mapping for adc in addition, a zero cross detect circuit is provided for the input pga, controlled by bit 8 in each attenuation register. this minimises audible clicks and zipper noise by updating the gain when the signal crosses the zero level.
product preview WM8776 w pp rev 1.91 june 2004 31 in addition a zero cross detect circuit is provided for the output pga volume under the control of bit 7 (zcen) in the each attenuation register. when zcen is set the attenuation values are only updated when the input signal to the gain stage is close to the analogue ground level. this minimises audible clicks and zipper noise as the gain values change. a timeout clock is also provided which will generate an update after a minimum of 131072 master clocks (= ~10.5ms with a master clock of 12.288mhz). the timeout clock may be disabled by setting tod. left and right inputs may also be independently muted. the lrboth control bit allows the user to write the same attenuation value to both left and right volume control registers, saving on software writes. the adc volume and mute also applies to the bypass signal path. register address bit label default description 7:0 lag[7:0] 11001111 (0db) attenuation data for left channel adc gain in 0.5db steps. see table 15. r14 (0eh) 0001110 attenuation adcl 8 zcla 0 left channel adc zero cross enable: 0: zero cross disabled 1: zero cross enabled 7:0 rag[7:0] 11001111 (0db) attenuation data for right channel adc gain in 0.5db steps. see table 15. r15 (0fh) 0001111 attenuation adcr 8 zcra 0 right channel adc zero cross enable: 0: zero cross disabled 1: zero cross enabled r21 (15h) 0010101 adc input mux 8 lrboth 0 right channel input pga controlled by left channel register 0 : right channel uses rag. 1 : right channel uses lag. 7 mutela 0 mute for left channel adc 0: mute off 1: mute on r21 (15h) 0010101 adc input mux 6 mutera 0 mute for right channel adc 0: mute off 1: mute on adc highpass filter disable the adc digital filters contain a digital high pass filter. this defaults to enabled and can be disabled using software control bit adchpd. register address bit label default description r11 (0bh) 0001011 adc control 8 adchpd 0 adc high pass filter disable: 0: high pass filter enabled 1: high pass filter disabled
WM8776 product preview w pp rev 1.91 june 2004 32 limiter / automatic level control (alc) the WM8776 has an automatic pga gain control circuit, which can function as a peak limiter or as an automatic level control (alc). in peak limiter mode, a digital peak detector detects when the input signal goes above a predefined level and will ramp the pga gain down to prevent the signal becoming too large for the input range of the adc. when the signal returns to a level below the threshold, the pga gain is slowly returned to its starting level. the peak limiter cannot increase the pga gain above its static level. figure 22 limiter operation in alc mode, the circuit aims to keep a constant recording volume irrespective of the input signal level. this is achieved by continuously adjusting the pga gain so that the signal level at the adc input remains constant. a digital peak detector monitors the adc output and changes the pga gain if necessary. figure 23 alc operation hold time decay time attack time input signal signal after alc pga gain alc target level input signal signal after pga pga gain limiter threshold attack time decay time
product preview WM8776 w pp rev 1.91 june 2004 33 the gain control circuit is enabled by setting the lcen control bit. the user can select between limiter mode and three different alc modes using the lcsel control bits. register address bit label default description r17 (11h) 0010001 alc control 2 8 lcen 0 enable the pga gain control circuit. 0 = disabled 1 = enabled r16 (10h) 0010000 alc control 1 8:7 lcsel 00 lc function select 00 = limiter 01 = alc right channel only 10 = alc left channel only 11 = alc stereo the limiter function only operates in stereo, which means that the peak detector takes the maximum of left and right channel peak values, and any new gain setting is applied to both left and right pgas, so that the stereo image is preserved. however, the alc function can also be enabled on one channel only. in this case, only one pga is controlled by the alc mechanism, while the other channel runs independently with its pga gain set through the control register. when enabled, the threshold for the limiter or target level for the alc is programmed using the lct control bits. this allows the threshold/target level to be programmed between -1db and -16db in 1db steps. register address bit label default description r16 (10h) 0010000 alc control 1 3:0 lct[3:0] 1011 (-5db) limiter threshold/alc target level in 1db steps. 0000: -16db fs 0001: -15db fs 1101: -3db fs 1110: -2db fs 1111: -1db fs attack and decay times the limiter and alc have different attack and decay times which determine their operation. however, the attack and decay times are defined slightly differently for the limiter and for the alc. dcy and atk control the decay and attack times, respectively. decay time (gain ramp-up). when in alc mode, this is defined as the time that i t takes for the pga gain to ramp up across 90% of its range (e.g. from C21db up to +20 db). when in limiter mode, it is defined as the time it takes for the gain to ramp up by 6db. the decay time can be programmed in power-of-two (2 n ) steps. for the alc this gives times from 33.6ms, 67.2ms, 134.4ms etc. to 34.41s. for the limiter this gives times from 1.2ms, 2.4ms etc., up to 1.2288s. attack time (gain ramp-down) when in alc mode, this is defined as the time that it takes for the pga gain to ramp down across 90% of its range (e.g. from +20db down to -21db gain). when in limiter mode, it is defined as the time it takes for the gain to ramp down by 6db. the attack time can be programmed in power-of-two (2 n ) steps, from 8.4ms, 16.8ms, 33.6ms etc. to 8.6s for the alc and from 250us, 500us, etc. up to 256ms. the time it takes for the recording level to return to its target value or static gain value therefore depends on both the attack/decay time and on the gain adjustment required. if the gain adjustment is small, it will be shorter than the attack/decay time.
WM8776 product preview w pp rev 1.91 june 2004 34 register address bit label default description lc attack (gain ramp-down) time 3:0 atk[3:0] 0010 alc mode 0000: 8.4ms 0001: 16.8ms 0010: 33.6ms (time doubles with every step) 1010 or higher: 8.6s limiter mode 0000: 250us 0001: 500us 0010: 1ms (time doubles with every step) 1010 or higher: 256ms lc decay (gain ramp-up) time r18 (12h) 0010010 alc control 3 7:4 dcy [3:0] 0011 alc mode 0000: 33.5ms 0001: 67.2ms 0010: 134.4ms .(time doubles for every step) 1010 or higher: 34.3ms limiter mode 0000: 1.2ms 0001: 2.4ms 0010: 4.8ms .(time doubles for every step) 1010 or higher: 1.2288s transient window (limiter only) to prevent the limiter responding to to short duration high ampitude signals (such as hand- claps in a live performance), the limiter has a programmable transient window preventing it responding to signals above the threshold until their duration exceeds the window period. the transient window is set in register tranwin. register address bit label default description r20 (14h) 0010100 limiter control 6:4 tranwin [2:0] 010 length of transient window 000: 0us (disabled) 001: 62.5us 010: 125us .. 111: 4ms zero cross the pga has a zero cross detector to prevent gain changes introducing noise to the signal. in alc mode the register bit alczc allows this to be turned off if desired. register address bit label default description r17 (11h) 0010001 alc control 2 7 alczc 0 (disabled) pga zero cross enable 0 : disabled 1: enabled
product preview WM8776 w pp rev 1.91 june 2004 35 maximum gain (alc only) and maximum attenuation to prevent low level signals being amplified too much by the alc, the maxgain register sets the upper limit for the gain. this prevents low level noise being over-amplified. the maxgain register has no effect on the limiter operation. the maxatten register has different operation for the limiter and for the alc. for the limiter it defines the maximum attenuation below the static (user programmed) gain. for the alc, it defines the lower limit for the gain. register address bit label default description r16 (10h) 0010000 alc control 1 6:4 maxgain 111 (+24db) set maximum gain for the pga (alc only) 111 : +24db 110 : +20db ..(-4db steps) 010 : +4db 001 : 0db 000 : 0db maximum attenuation of pga r20 (14h) 0010100 limiter control 3:0 maxatten 0110 limiter (attenuation below static) 0011 or lower: -3db 0100: -4db . (-1db steps) 1100 or higher: -12db alc (lower pga gain limit) 1010 or lower: -1db 1011 : -5db .. (-4db steps) 1110 : -17db 1111 : -21db hold time (alc only) the alc also has a hold time, which is the time delay between the peak level detected being below target and the pga gain beginning to ramp up. it can be programmed in power-of-two (2 n ) steps, e.g. 2.67ms, 5.33ms, 10.67ms etc. up to 43.7ms. alternatively, the hold time can also be set to zero. the hold time only applies to gain ramp-up, there is no delay before ramping the gain down when the signal level is above target. register address bit label default description r17 (11h) 0010001 alc control 2 3:0 hld[3:0] 0000 alc hold time before gain is increased. 0000: 0ms 0001: 2.67ms 0010: 5.33ms (time doubles with every step) 1111: 43.691s overload detector (alc only) to prevent clipping when a large signal occurs just after a period of quiet, the alc circuit includes an overload detector. if the adc input signal exceeds 87.5% o f full scale (C1. 16db), the pga gain is ramped down at the maximum attack rate (as when atk = 0000), until the signal level falls below 87.5% of full scale. this function is automatically enabled whenever the alc is enabled. (note: if atk = 0000, then the overload detector makes no difference to the operation of the alc. it is designed to prevent clipping when long attack times are used).
WM8776 product preview w pp rev 1.91 june 2004 36 noise gate (alc only) when the signal is very quiet and consists mainly of noise, the alc function may cause noise pumping, i.e. loud hissing noise during silence periods. the WM8776 has a noise gate function that prevents noise pumping by comparing the signal level a t the ainl1/2/3/4/5 and/or ainr1/2/3/4/5 pins against a noise gate threshold, ngth. the noise gate cuts in when: ? signal level at adc [db] < ngth [db] + pga gain [db] + mic boost gain [db] this is equivalent to: ? signal level at input pin [db] < ngth [db] when the noise gate is triggered, the pga gain is held constant (preventing it from ramping up as it would normally when the signal is quiet). the table below summarises the noise gate control register. the ngth control bits set the noise gate threshold with respect to the adc full-scale range. the threshold is adjusted in 6db steps. levels at the extremes of the range may cause inappropriate operation, so care should be taken with setCup of the function. note that the noise gate only works in conjunction with the alc function, and always operates on the same channel(s) as the alc (left, right, both, or none). register address bit label default description 0 ngat 0 noise gate function enable 1 = enable 0 = disable r19 (13h) 0010011 noise gate control 4:2 ngth[2:0] 000 noise gate threshold (with respect to adc output level) 000: -78dbfs 001: -72dbfs 6 db steps 110: -42dbfs 111: -36dbfs
product preview WM8776 w pp rev 1.91 june 2004 37 adc input mixer and powerdown control register address bit label default description r21 (15h) 0010101 adc input mux 4:0 amx[4:0] 00001 adc left channel input mixer control bits (see table 16) r13 (0dh) 0001101 powerdown control 6 ainpd 0 input mux and buffer powerdown 0: input mux and buffer enabled 1: input mux and buffer powered down register bits amx[4:0] control the left and right channel inputs into the stereo adc. the default is ain1. one bit of amx is allocated to each stereo input pair to allow the signals to be mixed before being digitised by the adc. for example, if amx[4:0] is 00101, the input signal to the adc will be (ain1l+ain3l) on the left channel and (ain1r+ain3r) on the right channel. however if the analogue input buffer is powered down, by setting ainpd, then all 5-channel mixer inputs are switched to buffered vmidadc. amx[4:0] left adc input right adc input 00001 ain1l ain1r 00010 ain2l ain2r 00100 ain3l ain3r 01000 ain4l ain4r 10000 ain5l ain5r table 16 adc input mixer ain1l/r ain2l/r ain3l/r ain4l/r ain5l/r amx[0] amx[1] amx[2] amx[3] amx[4] figure 24 adc input mixer
WM8776 product preview w pp rev 1.91 june 2004 38 output select and enable control register bits mx controls the output selection. the output select block consists of a summing stage and an input select switch for each input allowing each signal to be output individually or summed with other signals and output on the analogue output. the default for the output is dac playback only. vout may be selected to output dac playback, aux, analogue bypass or a sum of these using the output select controls mx[2:0]. for example, to select sum of dac and aux, set mx[2:0] to 011. the output mixer is powered down with dacd. register address bit label default description r22 (16h) 0010110 output mux 2:0 mx[2:0] 001 (dac playback) vout output select (see figure 25) figure 25 mx[2:0] output select software register reset writing any value to register 0010111 will cause a register reset, resetting all register bits to their default values.
product preview WM8776 w pp rev 1.91 june 2004 39 register map the complete register map is shown below. the detailed description can be found in the relevant text of the device description. the WM8776 can be configured using the control interface. all unused bits should be set to 0. register b 15 b 14 b 13 b 12 b 11 b 10 b 9 b8 b7 b6 b5 b4 b3 b2 b1 b0 default (hex) r0 (00h) 0 0 0 0 0 0 0 update hplzcen hpla[6:0] 079 r1 (01h) 0 0 0 0 0 0 1 update hprzcen hpra[6:0] 079 r2 (02h) 0 0 0 0 0 1 0 u pdatea hpmzcen hpmasta[6:0] 079 r3 (03h) 0 0 0 0 0 1 1 u pdated lda[7:0] 0ff r4 (04h) 0 0 0 0 1 0 0 u pdated rda[7:0] 0ff r5 (05h) 0 0 0 0 1 0 1 u pdated mastda 0ff r6 (06h) 0 0 0 0 1 1 0 0 0 0 0 0 0 0 phase[1:0] 000 r7 (07h) 0 0 0 0 1 1 1 0 pl[3:0] tod izd atc dzcen 090 r8 (08h) 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 dmute 000 r9 (09h) 0 0 0 1 0 0 1 0 0 0 0 0 0 dzfm [1:0] deemph 000 r10 (0ah) 0 0 0 1 0 1 0 0 0 0 dacwl[1:0] dacbcp daclrp dacfmt[1:0] 022 r11 (0bh) 0 0 0 1 0 1 1 adchpd 0 adcmclk adcwl[1:0] adcbcp adclrp adcfmt[1:0] 022 r12 (0ch) 0 0 0 1 1 0 0 adcms dacms dacrate[2:0] adcosr adcrate[2:0] 022 r13 (odh) 0 0 0 1 1 0 1 0 0 ainpd 0 0 hppd dacpd adcpd pdwn 008 r14 (0eh) 0 0 0 1 1 1 0 zcla lag[7:0] 0cf r15 (0fh) 0 0 0 1 1 1 1 zcra rag[7:0] 0cf r16 (10h) 0 0 1 0 0 0 0 lcsel[1:0] maxgain[2:0] lct[3:0] 07b r17 (11h) 0 0 1 0 0 0 1 lcen alczc 0 0 0 hld[3:0] 000 r18 (12h) 0 0 1 0 0 1 0 fdecay dcy[3:0] atk[3:0] 032 r19 (13h) 0 0 1 0 0 1 1 0 0 0 0 ngth[2:0] 0 ngat 000 r20 (14h) 0 0 1 0 1 0 0 0 0 tranwin[2:0] maxatten[3:0] 0a6 r21 (15h) 0 0 1 0 1 0 1 lrboth mutela mutera 0 amx[4:0] 001 r22 (16h) 0 0 1 0 1 1 0 0 0 0 mx[2:0] 001 r23 (17h) 0 0 1 0 1 1 1 software reset not reset
WM8776 product preview w pp rev 1.91 june 2004 40 register address bit label default description 6:0 hpla[6:0] 1111001 (0db) attenuation data for headphone left channel in 1db steps. 7 hplzcen 0 left headphone zero cross detect enable 0: zero cross disabled 1: zero cross enabled r0 (00h) 0000000 headphone analogue attenuation headphone left 8 update not latched controls simultaneous update of all attenuation latches 0: store hpla in intermediate latch (no change to output) 1: store hpla and update attenuation on all channels. 6:0 hpra[6:0] 1111001 (0db) attenuation data for headphone right channel in 1db steps. 7 hprzcen 0 right headphone zero cross detect enable 0: zero cross disabled 1: zero cross enabled r1 (01h) 0000001 headphone analogue attenuation headphone right 8 update not latched controls simultaneous update of all attenuation latches 0: store hpra in intermediate latch (no change to output) 1: store hpra and update attenuation on all channels. 6:0 hpmasta[6:0] 1111001 (0db) attenuation data for all analogue gains (l and r channels) in 1db steps. 7 mzcen 0 master zero cross detect enable 0: zero cross disabled 1: zero cross enabled r2 (02h) 0000010 headphone m aster analogue attenuation (all channels) 8 update not latched controls simultaneous update of all attenuation latches 0: store gains in intermediate latch (no change to output) 1: store gains and update attenuation on all channels. 7:0 lda1[7:0] 11111111 (0db) digital attenuation data for left channel dacl in 0.5db steps. r3 (03h) 0000011 digital attenuation dacl 8 update not latched controls simultaneous update of all attenuation latches 0: store lda1 in intermediate latch (no change to output) 1: store lda1 and update attenuation on all channels 7:0 rda1[6:0] 11111111 (0db) digital attenuation data for right channel dacr in 0.5db steps. r4 (04h) 0000100 digital attenuation dacr 8 update not latched controls simultaneous update of all attenuation latches 0: store rda1 in intermediate latch (no change to output) 1: store rda1 and update attenuation on all channels. 7:0 mastda[7:0] 11111111 (0db) digital attenuation data for all dac channels in 0.5db steps. r5 (05h) 0000101 master digital attenuation (all channels 8 update not latched controls simultaneous update of all attenuation latches 0: store gain in intermediate latch (no change to output) 1: store gain and update attenuation on all channels.
product preview WM8776 w pp rev 1.91 june 2004 41 register address bit label default description r6 (06h) 0000110 phase swaps 1:0 phase 00 controls phase of dac outputs (left, right channel) 0: sets non inverted output phase 1: inverts phase of dac output 0 dzcen 0 dac digital volume zero cross enable: 0: zero cross detect disabled 1: zero cross detect enabled 1 atc 0 attenuator control 0: all dacs use attenuations as programmed. 1: right dac uses left dac attenuations 2 izd 0 infinite zero detection circuit control and automute control 0: infinite zero detect automute disabled 1: infinite zero detect automute enabled 3 tod 0 dac and adc analogue zero cross detect timeout disable 0 : timeout enabled 1: timeout disabled dac output control pl[3:0] left output right output pl[3:0] left output right output 0000 mute mute 1000 mute right 0001 left mute 1001 left right 0010 right mute 1010 right right 0011 (l+r)/2 mute 1011 (l+r)/2 right 0100 mute left 1100 mute (l+r)/2 0101 left left 1101 left (l+r)/2 0110 right left 1110 right (l+r)/2 r7 (07h) 0000111 dac control 7:4 pl[3:0] 1001 0111 (l+r)/2 left 1111 (l+r)/2 (l+r)/2 r8 (08h) 0001000 dac mute 0 dmute 0 dac channel soft mute enables: 0: mute disabled 1: mute enabled 0 deemph 0 de-emphasis mode select: 0 : normal mode 1: de-emphasis mode dzfm zflag1 zflag2 r9 (09h) 0001001 dac control 2:1 dzfm 00 00 01 10 11 disabled left channels zero both channels zero either channel zero disabled right channels zero both channels zero either channel zero
WM8776 product preview w pp rev 1.91 june 2004 42 register address bit label default description 1:0 dacfmt[1:0] 10 dac interface format select 00: right justified mode 01: left justified mode 10: i 2 s mode 11: dsp mode daclrc polarity or dsp early/late mode select 2 daclrp 0 left justified / right justified / i 2 s 0: standard daclrc polarity 1: inverted daclrc polarity dsp mode 0: early mode 1: late mode 3 dacbcp 0 dac bitclk polarity 0: normal C din and daclrc sampled on rising edge of dacbclk. 1: inverted - din and daclrc sampled on falling edge of dacbclk. r10 (0ah) 0001010 dac interface control 5:4 dacwl[1:0] 10 dac input word length 00: 16-bit mode 01: 20-bit mode 10: 24-bit mode 11: 32-bit mode (not supported in right justified mode) 1:0 adcfmt[1:0] 10 adc interface format select 00: right justified mode 01: left justified mode 10: i 2 s mode 11: dsp mode adclrc polarity or dsp early/late mode select 2 adclrp 0 left justified / right justified / i 2 s 0: standard adclrc polarity 1: inverted adclrc polarity dsp mode 0: early mode 1: late mode 3 adcbcp 0 adc bitclk polarity 0: normal - adclrc sampled on rising edge of adcbclk; dout changes on falling edge of adcbclk. 1: inverted - adclrc sampled on falling edge of adcbclk; dout changes on rising edge of adcbclk. 5:4 adcwl[1:0] 10 adc input word length 00: 16-bit mode 01: 20-bit mode 10: 24-bit mode 11: 32-bit mode (not supported in right justified mode) 6 adcmclk 0 adcmclk polarity: 0: non-inverted 1: inverted r11 (0bh) 0001011 adc interface control 8 adchpd 0 adc highpass filter disable: 0: highpass filter enabled 1: highpass filter disabled
product preview WM8776 w pp rev 1.91 june 2004 43 register address bit label default description 2:0 adcrate[2:0] 010 master mode adcmclk:adclrc ratio select: 010: 256fs 011: 384fs 100: 512fs 3 adcosr 0 adc oversample rate select 0: 128x oversampling 1: 64x oversapmling 6:4 dacrate[2:0] 010 master mode dacmclk:daclrc ratio select: 000: 128fs 001: 192fs 010: 256fs 011: 384fs 100: 512fs 7 dacms 0 dac maser/slave interface mode select 0: slave mode C daclrc and dacbclk are inputs 1: master mode Cdaclrc and dacbclk are outputs r12 (0ch) 0001100 master mode control 8 adcms 0 adc maser/slave interface mode select 0: slave mode C adclrc and adcbclk are inputs 1: master mode C adclrc and adcbclk are outputs 0 pdwn 0 chip powerdown control (works in tandem with adcd and dacd): 0: all circuits running, outputs are active 1: all circuits in power save mode, outputs muted 1 adcpd 0 adc powerdown: 0: adc enabled 1: adc disabled 2 dacpd 0 dac powerdown 0: dac enabled 1: dac disabled 3 hppd 1 headphone output/pgas powerdown 0: headphone out enabled 1: headphone out disabled r13 (0dh) 0001101 pwr down control 6 ainpd 0 ainpd powerdown 0: analogue input enabled 1: analogue input disabled 7:0 lag[7:0] 11001111 (0db) attenuation data for left channel adc gain in 0.5db steps. 00000000 : digital mute 00000001 : -103db .. 11001111 : 0db 11111110 : +23.5db 11111111 : +24db r14 (0eh) 0001110 attenuation adcl 8 zcla 0 left adc zero cross enable: 0: zero cross disabled 1: zero cross enabled
WM8776 product preview w pp rev 1.91 june 2004 44 register address bit label default description 7:0 rag[7:0] 11001111 (0db) attenuation data for right channel adc gain in 0.5db steps. 00000000 : digital mute 00000001 : -103db .. 11001111 : 0db 11111110 : +23.5db 11111111 : +24db r15 (0fh) 0001111 attenuation adcr 8 zcra 0 right adc zero cross enable: 0: zero cross disabled 1: zero cross enabled 3:0 lct[3:0] 1011 (-5db) limiter threshold/alc target level in 1db steps 0000: -16db fs 0001: -15db fs 1101: -3db fs 1110: -2db fs 1111: -1db fs 6:4 maxgain[2:0] 111 (+24db) set maximum gain of pga 111 : +24db 110 : +20db .(-4db steps) 010 : +4db 001 : 0db 000 : 0db r16 (10h) 0010000 alc control 1 8:7 lcsel[1:0] 00 (limiter) alc/limiter function select 00 = limiter 01 = alc right channel only 10 = alc left channel only 11 = alc stereo (pga registers unused) 3:0 hld[3:0] 0000 (off) alc hold time before gain is increased. 0000: off 0001: 2.67ms 0010: 5.33ms (time doubles with every step) 1111: 43.691s 7 alczc 0 (zero cross off) alc uses zero cross detection circuit. r17 (11h) 0010001 alc control 2 8 lcen 0 enable gain control circuit. 0 = disable 1 = enable
product preview WM8776 w pp rev 1.91 june 2004 45 register address bit label default description alc/limiter attack (gain ramp-down) time 3:0 atk[3:0] 0010 (33ms/1ms) alc mode 0000: 8.4ms 0001: 16.8ms 0010: 33.6ms (time doubles with every step) 1010 or higher: 8.6s limiter mode 0000: 250us 0001: 500us 0010: 1ms (time doubles with every step) 1010 or higher: 256ms alc/limiter decay (gain ramp up) time r18 (12h) 0011000 alc control 3 7:4 dcy[3:0] 0011 (268ms/ 9.6ms) alc mode 0000: 33.5ms 0001: 67.2ms 0010: 134.4ms .(time doubles for every step) 1010 or higher: 34.3ms limiter mode 0000: 1.2ms 0001: 2.4ms 0010: 4.8ms .(time doubles for every step) 1010 or higher: 1.2288s 0 ngat 0 noise gate enable (alc only) 0 : disabled 1 : enabled r19 (13h) 0010011 noise gate control 4:2 ngth 000 noise gate threshold 000: -78dbfs 001: -72dbfs 6 db steps 110: -42dbfs 111: -36dbfs maximum attenuation of pga 3:0 maxatten [3:0] 0110 limiter (attenuation below static) 0011 or lower: -3db 0100: -4db . (-1db steps) 1100 or higher: -12db alc (lower pga gain limit) 1010 or lower: -1db 1011 : -5db .. (-4db steps) 1110 : -17db 1111 : -21db r20 (14h) 0010100 limiter control 6:4 tranwin [2:0] 010 length of transient window 000: 0us (disabled) 001: 62.5us 010: 125us .. 111: 4ms 4:0 amx[4:0] 00001 adc left channel input mixer control bit amx[4:0] adc left in adc right in 00001 ain1l ain1r 00010 ain2l ain2l 00100 ain3l ain3r 01000 ain4l ain4r 10000 ain5l ain5r 6 mutera 0 mute for right channel adc 0: mute off 1: mute on r21 (15h) 0010101 adc mux control 7 mutela 0 mute for left channel adc 0: mute off 1: mute on
WM8776 product preview w pp rev 1.91 june 2004 46 register address bit label default description 8 lrboth 0 right channel input pga controlled by left channel register 0 : right channel uses rag and mutera. 1 : right channel uses lag and mutela. r22 (16h) 0010110 output mux 2:0 mx[2:0] 001 vout output select (analogue bypass enable / disable) 001: dac 010: aux 100: bypass r23 (17h) 0010111 software reset [8:0] reset not reset writing to this register will apply a reset to the device registers.
product preview WM8776 w pp rev 1.91 june 2004 47 digital filter characteristics parameter test conditions min typ max unit adc filter 0.01 db 0 0.4535fs passband -6db 0.5fs passband ripple 0.01 db stopband 0.5465fs stopband attenuation f > 0.5465fs -65 db group delay 22 fs dac filter 0.05 db 0.454fs passband -3db 0.4892 fs passband ripple 0.05 db stopband 0.546fs stopband attenuation f > 0.546fs -60 db group delay 19 fs table 17 digital filter characteristics dac filter responses -120 -100 -80 -60 -40 -20 0 0 0.5 1 1.5 2 2.5 3 frequency (fs) response (db) figure 26 dac digital filter frequency response C 44.1, 48 and 96khz -80 -70 -60 -50 -40 -30 -20 -10 0 10 0.4 0.45 0.5 0.55 0.6 frequency (fs) response (db) figure 27 dac digital filter transition band C 44.1, 48 and 96khz
WM8776 product preview w pp rev 1.91 june 2004 48 -0.2 -0.15 -0.1 -0.05 0 0.05 0.1 0.15 0.2 0 0.1 0.2 0.3 0.4 0.5 frequency (fs) response (db) figure 28 dac digital filter ripple C 44.1, 48 and 96khz -80 -60 -40 -20 0 0 0.2 0.4 0.6 0.8 1 response (db) frequency (fs) figure 29 dac digital filter frequency response C 192khz -1 -0.8 -0.6 -0.4 -0.2 0 0.2 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 response (db) frequency (fs) figure 30 dac digital filter ripple - 192khz adc filter responses -80 -60 -40 -20 0 0 0.5 1 1.5 2 2.5 3 response (db) frequency (fs) figure 31 adc digital filter frequency response -0.02 -0.015 -0.01 -0.005 0 0.005 0.01 0.015 0.02 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 response (db) frequency (fs) figure 32 adc digital filter ripple
product preview WM8776 w pp rev 1.91 june 2004 49 adc high pass filter the WM8776 has a selectable digital highpass filter to remove dc offsets. the filter response is characterised by the following polynomial. figure 33 adc highpass filter response 1 - z -1 1 - 0.9995z -1 h(z) = -15 -10 -5 0 0 0.0005 0.001 0.0015 0.002 response (db) frequency (fs)
WM8776 product preview w pp rev 1.91 june 2004 50 digital de-emphasis characteristics -10 -8 -6 -4 -2 0 0 2 4 6 8 10 12 14 16 response (db) frequency (khz) figure 34 de-emphasis frequency response (32khz) -3 -2.5 -2 -1.5 -1 -0.5 0 0.5 1 0 2 4 6 8 10 12 14 16 response (db) frequency (khz) figure 35 de-emphasis error (32khz) -10 -8 -6 -4 -2 0 0 5 10 15 20 response (db) frequency (khz) figure 36 de-emphasis frequency response (44.1khz) -0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4 0 5 10 15 20 response (db) frequency (khz) figure 37 de-emphasis error (44.1khz) -10 -8 -6 -4 -2 0 0 5 10 15 20 response (db) frequency (khz) figure 38 de-emphasis frequency response (48khz) -1 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1 0 5 10 15 20 response (db) frequency (khz) figure 39 de-emphasis error (48khz)
product preview WM8776 w pp rev 1.91 june 2004 51 applications information external circuit configuration in order to allow the use of 2v rms and larger inputs to the adc and aux inputs, a structure is used that uses external resistors to drop these larger voltages. this also increases the robustness of the circuit to external abuse such as esd pulses. figure 40 shows the adc input multiplexor circuit with external components allowing 2vrms inputs to be applied. ain1l 10k 10uf ain2l 10k 10uf ain3l 10k 10uf ain4l 10k 10uf ain5l 10k 10uf ain1r 10k 10uf ain2r 10k 10uf ain3r 10k 10uf ain4r 10k 10uf ain5r 10k 10uf source selector inputs ainvgr ainopr 5k ainvgl ainopl 5k figure 40 adc input multiplexor configuration 10k mx[0] mx[1] mx[2] 10k 10k 10k dacl/r bypassl/r auxl/r 10uf aux input figure 41 5.1 channel input multiplexor configuration
WM8776 product preview w pp rev 1.91 june 2004 52 recommended external components figure 42 external component diagram
product preview WM8776 w pp rev 1.91 june 2004 53 it is recommended that a low pass filter be applied to the output from the dac for hi-fi applications. typically a second order filter is suitable and provides sufficient attenuation of high frequency components (the unique low order, high bit count multi-bit sigma delta dac structure used in WM8776 produces much less high frequency output noise). this filter is typically also used to provide the 2x gain needed to provide the standard 2vrms output level from most consumer equipment. figure 43 shows a suitable post dac filter circuit, with 2x gain. alternative inverting filter architectures might also be used with as good results. + _ + +vs -vs 10uf 51 ? 7.5k ? 680pf 1.8k ? 10k ? 4.7k ? 4.7k ? 1.0nf figure 43 recommended post dac filter circuit to ensure that system pop noise is kept to a minimum when power is applied or removed, a transistor clamp circuit arrangement may be added to the output connectors o f the system. a recommended clamp circuit configuration is shown below. when the +vs power supply is applied, pnp transistor q10 of the trigger circuit is held on until capacitor c49 is fully charged. with transistor q10 held on, npn transistors q4 to q5 of the clamp circuits are also switched on holding the system outputs near to gnd. when capacitor c49 is fully charged transistors q10 and q4 to q5 are switched off setting the outputs active. when the +vs power supply is removed, pnp transistor q11 of the trigger circuit is switched on. in turn, transistors q4 to q5 of the clamp circuits are switched on holding the outputs of the evaluation board near to gnd until the rest of the circuitry on the board has settled. note: it is recommended that low vcesat switching transistors should be used in this circuit to ensure that the clamp is applied before the rest of the circuitry has time to power down. important: if a trigger circuit such as the one shown is to be used, it is important that the +vs supply drops quicker than any other supply to ensure that the outputs are clamped during the period when pop noise may occur.
WM8776 product preview w pp rev 1.91 june 2004 54 package dimensions notes: a. all linear dimensions are in millimeters. b. this drawing is subject to change without notice. c. body dimensions do not include mold flash or protrusion, not to exceed 0.25mm. d. meets jedec.95 ms- 026, variation = abc. refer to this specification for further details. dm004.c ft: 48 pin tqfp (7 x 7 x 1.0 mm) symbols dimensions (mm) min nom max a ----- ----- 1.20 a 1 0.05 ----- 0.15 a 2 0.95 1.00 1.05 b 0.17 0.22 0.27 c 0.09 ----- 0.20 d 9.00 bsc d 1 7.00 bsc e 9.00 bsc e 1 7.00 bsc e 0.50 bsc l 0.45 0.60 0.75 0 o 3.5 o 7 o tolerances of form and position ccc 0.08 ref: jedec.95, ms-026 25 36 e b 12 1 d1 d e1 e 13 24 37 48 a a2 a1 seating plane ccc c -c- c l
product preview WM8776 w pp rev 1.91 june 2004 55 important notice wolfson microelectronics plc (wm) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current. all products are sold subject to the wm terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. wm warrants performance of its products to the specifications applicable at the time of sale in accordance with wms standard warranty. testing and other quality control techniques are utilised to the extent wm deems necessary to support this warranty. specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. in order to minimise risks associated with customer applications, adequate design and operating safeguards must be used by the customer to minimise inherent or procedural hazards. wolfson products are not authorised for use as critical components in life support devices or systems without the express written approval of an officer of the company. life support devices or systems are devices or systems that are intended for surgical implant into the body, or support or sustain life, and whose failure to perform when properly used in accordance with instructions for use provided, can be reasonably expected to result in a significant injury to the user. a critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. wm assumes no liability for applications assistance or customer product design. wm does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of wm covering or relating to any combination, machine, or process in which such products or services might be or are used. wms publication of information regarding any third partys products or services does not constitute wms approval, license, warranty or endorsement thereof. reproduction of information from the wm web site or datasheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations and notices. representation or reproduction of this information with alteration voids all warranties provided for an associated wm product or service, is an unfair and deceptive business practice, and wm is not responsible nor liable for any such use. resale of wms products or services with statements different from or beyond the parameters stated by wm for that product or service voids all express and any implied warranties for the associated wm product or service, is an unfair and deceptive business practice, and wm is not responsible nor liable for any such use. address: wolfson microelectronics plc westfield house 26 westfield road edinburgh eh11 2qb united kingdom tel :: +44 (0)131 272 7000 fax :: +44 (0)131 272 7001 email :: sales@wolfsonmicro.com

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